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low cost, 300 mhz rail-to-rail amplifiers ad8061/ad8062/ad8063 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features low cost single (ad8061), dual (ad8062) single with disable (ad8063) rail-to-rail output swing low offset voltage: 6 mv high speed 300 mhz, ?3 db bandwidth (g = 1) 650 v/s slew rate 8.5 nv/hz at 5 v 35 ns settling time to 0.1% with 1 v step operates on 2.7 v to 8 v supplies input voltage range = ?0.2 v to +3.2 v with v s = 5 excellent video specs (r l = 150 , g = 2) gain flatness 0.1 db to 30 mhz 0.01% differential gain error 0.04 differential phase error 35 ns overload recovery low power 6.8 ma/amplifier typical supply current ad8063 400 a when disabled applications imaging photodiode preamps professional video and cameras hand sets dvds/cds base stations filters adc drivers connection diagrams 8 7 6 5 1 2 3 4 nc ?in +in (ad8063 only) +v s v out nc ?v s ad8061/ ad8063 nc = no connect (not to scale) 01065-001 disable v out1 ?in1 +in1 ?v s +v s v out2 ?in2 +in2 1 2 3 4 8 7 6 5 (not to scale) ad8062 01065-003 figure 1. 8-lead soic (r) figure 2. 8-lead soic (r)/msop (rm) +in +v s ?v s ad8063 1 2 3 6 4 ?in v out (not to scale) 5 disable 01065-002 +in +v s ?v s 1 2 3 4 ?in v out 5 ad8061 (not to scale) 01065-004 figure 3. 6-lead sot-23 (rt) figure 4. 5-lead sot-23 (rt) general description the ad8061, ad8062, and ad8063 are rail-to-rail output voltage feedback amplifiers offering ease of use and low cost. they have bandwidth and slew rate typically found in current feedback amplifiers. all have a wide input common-mode voltage range and output voltage swing, making them easy to use on single supplies as low as 2.7 v. despite being low cost, the ad8061, ad8062, and ad8063 provide excellent overall performance. for video applications their differential gain and phase errors are 0.01% and 0.04 into a 150 load, along with 0.1 db flatness out to 30 mhz. addi- tionally, they offer wide bandwidth to 300 mhz along with 650 v/s slew rate. the ad8061, ad8062, and ad8063 offer a typical low power of 6.8 ma/amplifier, while being capable of delivering up to 50 ma of load current. the ad8063 has a power-down disable feature that reduces the supply current to 400 a. these features make the ad8063 ideal for portable and battery-powered applications where size and power are critical. r f = 0 frequency (mhz) 3 ?12 11 normalized gain (db) ?6 100 10 0 ?3 ?9 k v o = 0.2v p-p r l = 1k v bias = 1v r f out in v bias 50 r l r f = 50 01065-005 figure 5. small signal response, r f = 0 , 50
ad8061/ad8062/ad8063 rev. d | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 maximum power dissipation ..................................................... 6 esd caution .................................................................................. 6 typical performance characteristics ............................................. 7 circuit description ......................................................................... 14 headroom considerations ........................................................ 14 overload behavior and recovery ............................................ 15 capacitive load drive ............................................................... 15 disable operation ...................................................................... 16 board layout considerations ................................................... 16 applications ..................................................................................... 17 single-supply sync stripper ...................................................... 17 rgb amplifier ............................................................................ 17 multiplexer .................................................................................. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 20 revision history 12/05rev. c to rev. d updated format..................................................................universal change to features and general description............................... 1 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 5/01rev. b to rev. c replaced tpc 9 with new graph .................................................... 7 11/00rev. a to rev. b 2/00rev. 0 to rev. a 11/99revision 0: initial version
ad8061/ad8062/ad8063 rev. d | page 3 of 20 specifications t a = 25c, v s = 5 v, r l = 1 k, v o = 1 v, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth g = 1, v o = 0.2 v p-p 150 320 mhz g = C1, +2, v o = 0.2 v p-p 60 115 mhz ?3 db large signal bandwidth g = 1, v o = 1 v p-p 280 mhz bandwidth for 0.1 db flatness g = 1, v o = 0.2 v p-p 30 mhz slew rate g = 1, v o = 2 v step, r l = 2 k 500 650 v/s g = 2, v o = 2 v step, r l = 2 k 300 500 v/s settling time to 0.1% g = 2, v o = 2 v step 35 ns noise/distortion performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p, r l = 1 k ?77 dbc f c = 20 mhz, v o = 2 v p-p, r l = 1 k ?50 dbc crosstalk, output to output f = 5 mhz, g = 2, ad8062 ?90 dbc input voltage noise f = 100 khz 8.5 nv/hz input current noise f = 100 khz 1.2 pa/hz differential gain error (ntsc) g = 2, r l = 150 0.01 % differential phase error (ntsc) g = 2, r l = 150 0.04 degrees third order intercept f = 10 mhz 28 dbc sfdr f = 5 mhz 62 db dc performance input offset voltage 1 6 mv t min to t max 2 6 mv input offset voltage drift 3.5 v/c input bias current 3.5 9 a t min to t max 4 9 a input offset current 0.3 4.5 a open-loop gain v o = 0.5 v to 4.5 v, r l = 150 68 70 db v o = 0.5 v to 4.5 v, r l = 2 k 74 90 db input characteristics input resistance 13 m input capacitance 1 pf input common-mode voltage range ?0.2 to +3.2 v common-mode rejection ratio v cm = C0.2 v to +3.2 v 62 80 db output characteristics output voltage swingload resistance r l = 150 0.3 0.1 to 4.5 4.75 v is terminated at midsupply r l = 2 k 0.25 0.1 to 4.9 4.85 v output current v o = 0.5 v to 4.5 v 25 50 ma capacitive load drive, v out = 0.8 v 30% overshoot: g = 1, r s = 0 25 pf g = 2, r s = 4.7 300 pf power-down disable turn-on time 40 ns turn-off time 300 ns disable voltageoff 2.8 v disable voltageon 3.2 v power supply operating range 2.7 5 8 v quiescent current per amplifier 6.8 9.5 ma supply current when disabled (ad8063 only) 0.4 ma power supply rejection ratio ?v s = 2.7 v to 5 v 72 80 db
ad8061/ad8062/ad8063 rev. d | page 4 of 20 t a = 25c, v s = 3 v, r l = 1 k, v o = 1 v, unless otherwise noted. table 2. parameter conditions min typ max unit dynamic performance C3 db small signal bandwidth g = 1, v o = 0.2 v p-p 150 300 mhz g = C1, +2, v o = 0.2 v p-p 60 115 mhz C3 db large signal bandwidth g = 1, v o = 1 v p-p 250 mhz bandwidth for 0.1 db flatness g = 1, v o = 0.2 v p-p 30 mhz slew rate g = 1, v o = 1 v step, r l = 2 k 190 280 v/s g = 2, v o = 1.5 v step, r l = 2 k 180 230 v/s settling time to 0.1% g = 2, v o = 1 v step 40 ns noise/distortion performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p, r l = 1 k ?60 dbc f c = 20 mhz, v o = 2 v p-p, r l = 1 k ?44 dbc crosstalk, output to output f = 5 mhz, g = 2 ?90 dbc input voltage noise f = 100 khz 8.5 nv/hz input current noise f = 100 khz 1.2 pa/hz dc performance input offset voltage 1 6 mv t min to t max 2 6 mv input offset voltage drift 3.5 v/c input bias current 3.5 8.5 a t min to t max 4 8.5 a input offset current 0.3 4.5 a open-loop gain v o = 0.5 v to 2.5 v, r l = 150 66 70 db v o = 0.5 v to 2.5 v, r l = 2 k 74 90 db input characteristics input resistance 13 m input capacitance 1 pf input common-mode voltage range ?0.2 to +12 v common-mode rejection ratio v cm = C0.2 v to +1.2 v 80 db output characteristics output voltage swing r l = 150 0.3 0.1 to 2.87 2.85 v r l = 2 k 0.3 0.1 to 2.9 2.90 v output current v o = 0.5 v to 2.5 v 25 ma capacitive load drive, v out = 0.8 v 30% overshoot, g = 1, r s = 0 25 pf g = 2, r s = 4.7 300 pf power-down disable turn-on time 40 ns turn-off time 300 ns disable voltageoff 0.8 v disable voltageon 1.2 v power supply operating range 2.7 3 v quiescent current per amplifier 6.8 9 ma supply current when disabled (ad8063 only) 0.4 ma power supply rejection ratio 72 80 db
ad8061/ad8062/ad8063 rev. d | page 5 of 20 t a = 25c, v s = 2.7 v, r l = 1 k, v o = 1 v, unless otherwise noted. table 3. parameter conditions min typ max unit dynamic performance C3 db small signal bandwidth g = 1, v o = 0.2 v p-p 150 300 mhz g = C1, +2, v o = 0.2 v p-p 60 115 mhz g = 1, v o = 1 v p-p 230 mhz bandwidth for 0.1 db flatness g = 1, v o = 0.2 v p-p, v o dc = 1 v 30 mhz slew rate g = 1, v o = 0.7 v step, r l = 2 k 110 150 v/s g = 2, v o = 1.5 v step, r l = 2 k 95 130 v/s settling time to 0.1% g = 2, v o = 1 v step 40 ns noise/distortion performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p, r l = 1 k C60 dbc f c = 20 mhz, v o = 2 v p-p, r l = 1 k C44 dbc crosstalk, output to output f = 5 mhz, g = 2 C90 dbc input voltage noise f = 100 khz 8.5 nv/hz input current noise f = 100 khz 1.2 pa/hz dc performance input offset voltage 1 6 mv t min to t max 2 6 mv input offset voltage drift 3.5 v/c input bias current 3.5 a t min to t max 4 8.5 a input offset current 0.3 4.5 a open-loop gain v o = 0.5 v to 2.2 v, r l = 150 63 70 db v o = 0.5 v to 2.2 v, r l = 2 k 74 90 db input characteristics input resistance 13 m input capacitance 1 pf input common-mode voltage range C0.2 to +0.9 v common-mode rejection ratio v cm = C0.2 v to +0.9 v 0.8 db output characteristics output voltage swing r l = 150 0.3 0.1 to 2.55 2.55 v r l = 2 k 0.25 0.1 to 2.6 2.6 v output current v o = 0.5 v to 2.2 v 25 ma capacitive load drive, v out = 0.8 v 30% overshoot: g = 1, r s = 0 25 pf g = 2, r s = 4.7 300 pf power-down disable turn-on time 40 ns turn-off time 300 ns disable voltageoff 0.5 v disable voltageon 0.9 v power supply operating range 2.7 8 v quiescent current per amplifier 6.8 8.5 ma supply current when disabled (ad8063 only) 0.4 ma power supply rejection ratio 80 db
ad8061/ad8062/ad8063 rev. d | page 6 of 20 absolute maximum ratings table 4. parameter rating supply voltage 8 v internal power dissipation 1 8-lead soic (r) 0.8 w 5-lead sot-23 (rt) 0.5 w 6-lead sot-23 (rt) 0.5 w 8-lead msop (rm) 0.6 w input voltage (common-mode) (?v s ? 0.2 v) to (+v s ? 1.8 v) differential input voltage v s output short-circuit duration observe power derating curves storage temperature range r-8, rm-8, sot-23-5, sot-23-6 ?65c to +125c operating temperature range ?40c to +85c lead temperature range (soldering 10 sec) 300c 1 specification is for device in free air. 8-lead soic: ja = 160c/w; jc = 56c/w. 5-lead sot-23: ja = 240c/w; jc = 92c/w. 6-lead sot-23: ja = 230c/w; jc = 92c/w. 8-lead msop: ja = 200c/w; jc = 44c/w. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissipation the maximum power that can be safely dissipated by the ad806x is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junc- tion temperature of 175c for an extended period can result in device failure. while the ad806x is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves. ambient temperature ( c) 2.0 1.0 0 ?50 ?40 maximum power dissipation (w) ?30 70 80 90 1.5 0.5 60504030 0 ?10?20 2010 t j = 150 c msop sot-23-5, -6 8-lead soic package 01065-006 figure 6. maximum power dissipation vs. temperature for ad8061/ad8062/ad8063 esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8061/ad8062/ad8063 rev. d | page 7 of 20 typical performance characteristics load current (ma) 0 0 10 voltage differential from v s 0.2 +v out @ +85 c +v out @ +25 c +v out @ ?40 c ?v out @ +85 c ?v out @ +25 c ?v out @ ?40 c 0.4 0.6 0.8 1.0 1.2 20 30 40 50 60 70 80 90 01065-007 figure 7. output saturation voltage vs. load current single power supply (v) 18 8 0 power supply current (ma) 16 14 12 10 6 4 2 ad8062 ad8061 01065-008 2 8 7 5 46 3 figure 8. i supply vs. v supply r f = 0 frequency (mhz) 3 ?12 1 1k normalized gain (db) ?6 100 10 0 ?3 ?9 v o = 0.2v p-p r l = 1k v bias = 1v r f out in v bias 50 r l r f = 50 01065-009 figure 9. small signal response, r f = 0 , 50 frequency (mhz) 3 ?12 1 1k normalized gain (db) ?6 100 10 0 ?3 ?9 g = 1 g = 2 g = 5 v o = 0.2v p-p r l = 1k v bias = 1v 01065-010 figure 10. small signal frequency response frequency (mhz) 3 ?12 1 1k normalized gain (db) ?6 100 10 0 ?3 ?9 g = 2 g = 5 g = 1 v o = 1.0v p-p r l = 1k v bias = 1v 01065-011 figure 11. large signal frequency response g = ?1 frequency (mhz) 3 ?12 1 1k normalized gain (db) ?6 100 10 0 ?3 ?9 g = ?2 g = ?5 v s = 5v v o = 0.2v p-p r l = 1k v bias = 1v r f out in v bias 50 r l 01065-012 figure 12. small signal frequency response
ad8061/ad8062/ad8063 rev. d | page 8 of 20 frequency (mhz) 3 ?12 1 1k normalized gain (db) ?6 100 10 0 ?3 ?9 g = ?1 g = ?2 g = ?5 v s = 5v v o = 1v p-p r l = 1k v bias = 1v 01065-013 figure 13. large signal frequency response frequency (mhz) 0.1 ?0.5 1 1k normalized gain (db) ?0.2 100 10 0 ?0.1 ?0.3 ?0.4 v s = 5v v s = 3v v s = 2.7v v o = 0.2v p-p r l = 1k v bias = 1v g = 1 01065-014 figure 14. 0.1 db flatness 0.01 0.1 1 10 100 1k 80 60 40 20 0 ?20 ?40 200 150 100 50 0 ?50 ?100 ?150 ?200 ?250 ?300 open-loop gain (db) phase (degrees) frequency (mhz) series 2 series 1 01065-015 figure 15. ad8062 open-loop ga in and phase vs. frequency, v s = 5 v, r l = 1 k input signal bias (v) 0 ?50 ?100 0.5 harmonic distortion (dbc) 1.0 3.0 3.5 ?10 ?20 ?30 ?40 ?60 ?70 ?80 ?90 2.5 2.0 1.5 3rd @ 1mhz 3rd @ 10mhz 2nd @ 1mhz 2nd @ 10mhz v s = 5v r l = 1k g = 1 01065-016 figure 16. harmonic distor tion for a 1 v p-p signal vs. input signal dc bias frequency (mhz, start = 10khz, stop = 30mhz) ?70 0.01 distortion (db) ?40 ?50 ?60 ?80 ?90 ?100 ?110 0.1 3rd h 2nd h 1.25v dc 50 604 1k 52.3 0.1 f 10 f 5v + + ? 0.1 f 1k (r load ) 1m input 01065-017 1 10 50 figure 17. harmonic distortion for a 1 v p-p output signal vs. input signal dc bias output signal dc bias (v) ?50 ?120 0 distortion (db) 1 ?30 ?40 ?60 ?70 ?80 ?90 4 3 2 ?110 ?100 v s = 5v r l = 1k g = 5 v o = 1v p-p 3rd 2nd 10mhz 5mhz 2nd 3rd 1mhz 3rd 2nd 5 01065-018 figure 18. harmonic distortion vs. output signal dc bias
ad8061/ad8062/ad8063 rev. d | page 9 of 20 rto output (v p-p) ?100 distortion (db) 1.0 3.0 3.5 ?40 ?50 ?60 ?70 2.5 2.0 1.5 3rd @ 2mhz 2nd @ 2mhz 2nd @ 10mhz ?90 ?80 4.0 4.5 v s = 5v r f = r l = 1k g = 2 ?110 3rd @ 500khz + 1k 5v 10 f 0.1 f 1k 50 1k 50 1m input to 3589a 2nd @ 500khz 01065-019 figure 19. harmonic distortion vs. output signal amplitude frequency (mhz, start = 10khz, stop = 30mhz) distortion (db) 0.01 0.1 1 10 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 v s = 5v r i = r l = 1k v o = 2v p-p g = 2 s1 2nd harmonic/ dual 2.5v supply s1 3rd harmonic/ single +5v supply s1 2nd harmonic/ single +5v supply s1 3rd harmonic/ dual 2.5v supply ?110 01065-020 figure 20. harmonic distortion vs. frequency time ( s) 0.7 0 output voltage (v) 0.2 1.0 0.9 0.8 0.6 0.5 0.4 0.3 0.1 0 0.1 0.2 0.3 0.4 0.5 v s = 5v r l = 1k g = 1 01065-021 figure 21. 400 mv pulse response 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th differential phase (degrees) 0.02 0 ?0.02 ?0.04 ?0.06 differential gain (%) 0.01 0 ?0.01 ?0.02 ?0.04 ?0.06 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 01065-022 figure 22. differential gain and phase error, g = 2, ntsc input signal, r l = 1 k, v s = 5 v 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.04 0.03 0.02 0.01 0 0.010 0.005 0 ?0.005 ?0.010 ?0.01 ?0.02 differential phase (degrees) differential gain (%) 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 01065-023 figure 23. differential gain and phase error, g = 2, ntsc input signal, r l = 150 , v s = 5 v output step amplitude (v) 1000 500 slew rate (v/ s) 700 1.0 900 800 600 1.5 2.0 2.5 3.0 400 falling edge rising edge 100 300 200 0 v s = 5v r l = 1k g = 1 01065-024 figure 24. slew rate vs. output step amplitude
ad8061/ad8062/ad8063 rev. d | page 10 of 20 output step (v) 1400 0 4.0 slew rate (v/ s) 2.0 2.5 1200 1000 800 600 400 200 0 0.5 3.0 3.5 falling edge v s = +5v falling edge v s = 4v rising edge v s = 4v rising edge v s = +5v 1.0 1.5 01065-025 figure 25. slew rate vs. output step amplitude, g = 2, r l = 1 k, v s = 5 v voltage noise (nv/ hz) v s = 5v r l = 1k frequency (hz) 1k 10 10m 100 1k 100k 1m 100 10 1 10k 01065-026 figure 26. voltage noise vs. frequency frequency (hz) 100 10 10m current noise (pa/ hz) 100 1k 100k 1m 10 0 10k 1 v s =5v r l =1k 01065-027 figure 27. current noise vs. frequency 500mv/div 0 20 40 60 80 100 120 140 160 180 200 2.5v volts time (ns) 0v v in v out v s = 2.5v g = 1 r l = 1k 01065-028 figure 28. input overload recovery, input step = 0 v to 2 v 500mv/div v s = 2.5v g = 5 r l = 1k 0 20 40 60 80 100 120 140 160 180 200 2.5v volts time (ns) 1.0v 0v v in v out 01065-029 figure 29. output overload reco very, input step = 0 v to 1 v frequency (mhz) 0.01 500 cmrr (db) 0.1 10 100 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 side 1 side 2 v cm = 0.2v p-p r l = 100 v s = 2.5v 154 154 57.6 50 v in 200mv p-p 604 604 01065-030 figure 30. cmrr vs. frequency
ad8061/ad8062/ad8063 rev. d | page 11 of 20 psrr (db) frequency (mhz) 500 0.1 10 100 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 ? psrr +psrr v s = 0.2v p-p r l = 1k v s = 5v 0.01 01065-031 figure 31. psrr vs. frequency delta frequency (mhz) 0.01 500 output to output crosstalk (db) 0.1 10 100 ?120 ?110 ?100 ?80 ?70 ?60 ?50 ?40 ?30 ?20 1 input = side 2 input = side 1 v s = 5v v in = 400mv rms r l = 1k g = 2 ?90 in 1k 1k 50 +2.5v 1k out ?2.5v 01065-032 figure 32. ad8062 crosstalk, v out = 2.0 v p-p, r l = 1 k, g = 2, v s = 5 v frequency (mhz) 0 1 1k disabled isolation (db) ?20 100 10 ?10 ?30 ?50 ?40 ?60 ?70 ?80 ?90 v s = 5v v o = 0.2v p-p r l = 1k v bias = 1v 01065-033 figure 33. disabled output isolation frequency response disable voltage 7 1.0 5.0 i supply (ma) 1.5 2.0 2.5 6 5 4 3 1 0 3.0 2 3.5 4.0 4.5 v s = 5v 01065-034 figure 34. disable voltage vs. supply current v disable time ( s) 6 0 2.0 output voltage (v) 0.4 5 4 3 2 0 ?1 0.8 1 1.2 1.6 v out v s = 5v g = 2 f in = 10mhz @ 1.3v bias r l = 100 01065-035 figure 35. disable function, voltage = 0 v to 5 v frequency (mhz) 1k 0.1 1k impedance ( ) 10 1 10 100 100 1 0.1 0.01 v s = 5v v o = 0.2v p-p r l = 1k v bias = 1v 01065-036 figure 36. output impe dance vs. frequency, v out = 0.2 v p-p, r l = 1 k, v s = 5 v
ad8061/ad8062/ad8063 rev. d | page 12 of 20 20ns/div +0.1% settling time to 0.1% ?0.1% v s = 5v r l = 1k t = 0 1k 50 1k r l = 1k 01065-037 figure 37. output settling time to 0.1% output voltage step 50 0.5 settling time (ns) 1.0 1.5 2.0 45 40 35 30 25 20 15 10 5 0 2.5 falling edge rising edge v s = 5v r l = 1k g = 1 01065-038 figure 38. settling time vs. v out 2 s v s = 5v g = ?1 r f = 1k r l = 1k 4.86 2.43 0v 1v 01065-039 figure 39. output swing 500mv/div v s = 5v g = 2 r l = 1k v in = 1v p-p 0 10 20 80 90 100 3.5v time (ns) 2.5v 1.5v 7060504030 01065-040 figure 40. 1 v step response 20mv/div v s = 5v g = 2 r l = 1k v in = 100mv 0 10 20 80 90 100 2.6v time (ns) 2.5v 2.4v 7060504030 01065-041 figure 41. 100 mv step response 2 s/div 0v 1v/div v s = 5v g = 2 r f = r l = 1k v in = 4v p-p 01065-042 figure 42. output rail-to-rail swing
ad8061/ad8062/ad8063 rev. d | page 13 of 20 50mv/div v s = 5v g = 1 r l = 1k 0 5 10 40 45 50 2.6v time (ns) 2.5v 2.4v 3530252015 01065-043 1v/div v s = 5v g = 2 r l = r f = 1k v in = 2v p-p 0 5 10 40 45 50 time (ns) 3530252015 4.5v 2.5v 0.5v 01065-044 figure 44. 2 v step response figure 43. 200 mv step response
ad8061/ad8062/ad8063 rev. d | page 14 of 20 circuit description the ad8061/ad8062/ad8063 family is comprised of high speed voltage feedback op amps. the high slew rate input stage is a true, single-supply topology, capable of sensing signals at or below the minus supply rail. the rail-to-rail output stage can pull within 30 mv of either supply rail when driving light loads and within 0.3 v when driving 150 . high speed perform- ance is maintained at supply voltages as low as 2.7 v. headroom considerations these amplifiers are designed for use in low voltage systems. to obtain optimum performance, it is useful to understand the behavior of the amplifier as input and output signals approach the amplifiers headroom limits. the ad806xs input common-mode voltage range extends from the negative supply voltage (actually 200 mv below this), or ground for single-supply operation, to within 1.8 v of the positive supply voltage. thus, at a gain of 2, the ad806x can provide full rail-to-rail output swing for supply voltage as low as 3.6 v, assuming the input signal swing from ?v s (or ground) to +v s /2. at a gain of 3, the ad806x can provide a rail-to-rail output range down to 2.7 v total supply voltage. exceeding the headroom limit is not a concern for any inverting gain on any supply voltage, as long as the reference voltage at the amplifiers positive input lies within the amplifiers input common-mode range. the input stage is the headroom limit for signals when the amplifier is used in a gain of 1 for signals approaching the positive rail. figure 45 shows a typical offset voltage vs. input common-mode voltage for the ad806x amplifier on a 5 v supply. accurate dc performance is maintained from approximately 200 mv below the minus supply to within 1.8 v of the positive supply. for high-speed signals, however, there are other considerations. figure 46 shows ?3 db bandwidth vs. dc input voltage for a unity-gain follower. as the common-mode voltage approaches the positive supply, the amplifier holds together well, but the bandwidth begins to drop at 1.9 v within +v s . this manifests itself in increased distortion or settling time. figure 16 plots the distortion of a 1 v p-p signal with the ad806x amplifier used as a follower on a 5 v supply vs. signal common-mode voltage. distortion performance is maintained until the input signal center voltage gets beyond 2.5 v, as the peak of the input sine wave begins to run into the upper common-mode voltage limit. v cm (v) v os (mv) ?4.0 ?3.6 ?3.2 ?2.8 ?2.4 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 01065-045 figure 45. v os vs. common-mode voltage, v s = 5 v v cm = 3.0 frequency (mhz) 2 ?8 0.1 gain (db) ?4 0 ?2 ?6 1 10 100 1k 10k v cm = 3.1 v cm = 3.2 v cm = 3.3 v cm = 3.4 01065-046 figure 46. unity-gain follower ba ndwidth vs. input common mode, v s = 5 v higher frequency signals require more headroom than lower frequencies to maintain distortion performance. figure 47 illustrates how the rising edge settling time for the amplifier configured as a unity-gain follower stretches out as the top of a 1 v step input approaches and exceeds the specified input common-mode voltage limit. for signals approaching the minus supply and inverting gain and high positive gain configurations, the headroom limit is the output stage. the ad806x amplifiers use a common emitter style output stage. this output stage maximizes the available output range, limited by the saturation voltage of the output transistors. the saturation voltage increases with the drive current the output transistor is required to supply, due to the output transistors collector resistance. the saturation voltage is estimated using the equation v sat = 25 mv + i o 8 , where i o is the output current, and 8 is a typical value for the output transistors collector resistance.
ad8061/ad8062/ad8063 rev. d | page 15 of 20 time (ns) 2.0 0 output voltage (v) 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 4 8 12 16 20 24 28 32 2v to 3v step 2.1v to 3.1v step 2.2v to 3.2v step 2.3v to 3.3v step 2.4v to 3.4v step 01065-047 figure 47. output rising edge for 1 v step at input headroom limits, g = 1, v s = 5 v, 0 v as the saturation point of the output stage is approached, the output signal shows increasing amounts of compression and clipping. as in the input headroom case, the higher frequency signals require a bit more headroom than lower frequency signals. figure 16 , figure 17 , and figure 18 illustrate this point, plotting typical distortion vs. output amplitude and bias for gains of 2 and 5. overload behavior and recovery input the specified input common-mode voltage of the ad806x is ?200 mv below the negative supply to within 1.8 v of the positive supply. exceeding the top limit results in lower bandwidth and increased settling time as seen in figure 46 and figure 47 . pushing the input voltage of a unity-gain follower beyond 1.6 v within the positive supply leads to the behavior shown in figure 48 an increasing amount of output error and much increased settling time. recovery time from input voltages 1.6 v or closer to the positive supply is approxi- mately 35 ns, which is limited by the settling artifacts caused by transistors in the input stage coming out of saturation. the ad806x family does not exhibit phase reversal, even for input voltages beyond the voltage supply rails. going more than 0.6 v beyond the power supplies will turn on protection diodes at the input stage, which will greatly increase the devices current draw. time (ns) 2.1 0 output voltage (v) 2.3 100 voltage step from 2.4v to 3.4v 2.5 2.7 2.9 3.1 3.3 3.5 3.7 voltage step from 2.4v to 3.6v voltage step from 2.4v to 3.8v, 4v and 5v 200 300 400 500 600 01065-048 figure 48. pulse response for g = 1 follower, input step overloading the input stage output output overload recovery is typically within 40 ns after the amplifiers input is brought to a nonoverloading value. figure 49 shows output recovery transients for the amplifier recovering from a saturated output from the top and bottom supplies to a point at midsupply. time (ns) ? 0.2 input and output voltage (v) output voltage 5v to 2.5v 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 10 20 30 40 50 60 70 output voltage 0v to 2.5v input voltage edges r 5v v o 2.5v r v in ? ? 0 01065-049 figure 49. overload recovery, g = ?1, v s = 5 v capacitive load drive the ad806x family is optimized for bandwidth and speed, not for driving capacitive loads. output capacitance creates a pole in the amplifiers feedback path, leading to excessive peaking and potential oscillation. if dealing with load capacitance is a requirement of the application, the two strategies to consider are as follows: 1. use a small resistor in series with the amplifiers output and the load capacitance. 2. reduce the bandwidth of the amplifiers feedback loop by increasing the overall noise gain.
ad8061/ad8062/ad8063 rev. d | page 16 of 20 figure 50 shows a unity-gain follower using the series resistor strategy. the resistor isolates the output from the capacitance and, more importantly, creates a zero in the feedback path that compensates for the pole created by the output capacitance. vcc disable to amplifier bias vee 2v 01065-052 ad8061 v o r series c load v in 01065-050 figure 52. disable circuit of the ad8063 figure 50. series resistor isolating capacitive load figure 34 shows the ad8063 supply current vs. disable voltage. figure 35 plots the output seen when the ad8063 input is driven with a 10 mhz sine wave, and the disable is toggled from 0 v to 5 v, illustrating the parts turn-on and turn-off time. figure 33 shows the input/output isolation response with the ad8063 shut off. voltage feedback amplifiers like those in the ad806x family are able to drive more capacitive load without excessive peaking when used in higher gain configurations, because the increased noise gain reduces the bandwidth of the overall feedback loop. figure 51 plots the capacitance that produces 30% overshoot vs. noise gain for a typical amplifier. closed-loop gain 10k 1k 10 1 2 capacitive load (pf) 100 34 5 r s = 0 r s = 4.7 01065-051 board layout considerations maintaining the high speed performance of the ad806x family requires the use of high speed board layout techniques and low parasitic components. the pcb should have a ground plane covering unused portions of the component side of the board to provide a low impedance path. remove the ground plane near the package to reduce parasitic capacitance. proper bypassing is critical. use a ceramic 0.1 f chip capacitor to bypass both supplies. locate the chip capacitor within 3 mm of each power pin. additionally, connect in parallel a 4.7 f to 10 f tantalum electrolytic capacitor to provide charge for fast, large signal changes at the output. figure 51. capacitive load vs. closed-loop gain minimizing parasitic capacitance at the amplifiers inverting input pin is very important. locate the feedback resistor close to the inverting input pin. the value of the feedback resistor may come into playfor instance, 1 k interacting with 1 pf of parasitic capacitance creates a pole at 159 mhz. use stripline design techniques for signal traces longer than 25 mm. design them with either 50 or 75 characteristic impedance and proper termination at each end. disable operation the internal circuit for the ad8063 disable function is shown in figure 52 . when the disable node is pulled below 2 v from the positive supply, the supply current decreases from typically 6.5 ma to under 400 a, and the ad8063 output will enter a high impedance state. if the disable node is not connected and allowed to float, the ad8063 stays biased at full power.
ad8061/ad8062/ad8063 rev. d | page 17 of 20 applications single-supply sync stripper when a video signal contains synchronization pulses, it is sometimes desirable to remove them prior to performing certain operations. in the case of a-to-d conversion, the sync pulses consume some of the dynamic range, so removing them increases the converters available dynamic range for the video information. figure 53 shows a basic circuit for creating a sync stripper using the ad8061 powered by a single supply. when the negative supply is at ground potential, the lowest potential to which the output can go is ground. this feature is exploited to create a waveform whose lowest amplitude is the black level of the video and does not include the sync level. 75 video out 75 r g 1k 75 r f 1k 10 f 3v ad8061 0.1 f 3 2 4 6 7 v ideo in pin numbers are for 8-lead package 01065-053 figure 53. single 3 v sync stripper using ad8061 in this case, the input video signal has its black level at ground, so it comes out at ground at the input. since the sync level is below the black level, it will not show up at the output. however, all of the active video portion of the waveform will be amplified by a gain of two and then be normalized to unity gain by the back- terminated transmission line. figure 54 is an oscilloscope plot of the input and output waveforms. 01065-054 500mv input output 1 2 10 s figure 54. input and output wa veforms for a single-supply video sync stripper using an ad8061 some video signals with sync are derived from single-supply devices, such as video dacs. these signals can contain sync, but the whole waveform is positive, and the black level is not at ground but at some positive voltage. the circuit can be modified to provide the sync stripping function for such a waveform. instead of connecting r g to ground, connect it to a dc voltage that is two times the black level of the input signal. the gain from the +input to the output is two, which means the black level will be amplified by two to the output. however, the gain through r g is Cunity to the output. it takes a dc level of twice the input black level to shift the black level to ground at the output. when this occurs, the sync will be stripped, and the active video will be passed as in the ground-referenced case. 75 10 f 0.1 f 3v 3 2 4 6 7 75 monitor #1 75 75 75 1k 1k 1k 1k 3v 1k 3 2 5 6 7 8 1 4 monitor #2 green dac red green blue red dac blue dac 75 75 75 75 ad8061 75 10 f 0.1 f 1k ad8062 75 ad8062 75 01065-055 figure 55. rgb cable driver using ad8061 and ad8062 rgb amplifier most rgb graphics signals are created by video dac outputs that drive a current through a resistor to ground. at the video black level, the current goes to zero, and the voltage of the video is also zero. before the availability of high speed rail-to rail op amps, it was essential that an amplifier have a negative supply to amplify such a signal. such an amplifier is necessary if one wants to drive a second monitor from the same dac outputs. however, high speed, rail-to-rail output amplifiers like the ad8061 and ad8062 accept ground level input signals and output ground level signals. they are used as rgb signal amplifiers. a combination of the ad8061 (single) and the ad8062 (dual) amplifies the three video channels of an rgb system. figure 55 shows a circuit that performs this function.
ad8061/ad8062/ad8063 rev. d | page 18 of 20 the select signal and the output waveforms for this circuit are shown in figure 57 . for synchronization clarity, two differ- ent frequency synthesizers, whose time bases are locked to each other, generate the signals. multiplexer the ad8063 has a disable pin used to power down the ampli- fier to save power or to create a mux circuit. if two (or more) ad8063 outputs are connected together, and only one is enabled, then only the signal of the enabled amplifier will appear at the output. this configuration is used to select from various input signal sources. additionally, the same input signal is applied to different gain stages, or differently tuned filters, to make a gain- step amplifier or a selectable frequency amplifier. 1v 2v 2 s select output 01065-057 figure 56 shows a schematic of two ad8063s used to create a mux that selects between two inputs. one of these is a 1 v p-p, 3 mhz sine wave; the other is a 2 v p-p, 1 mhz sine wave. 49.9 1k +4v 1 ?4v 49.9 time base out time base in 1v p-p 3mhz 2 v p-p 1mhz v out 49.9 select hco4 1k 10 f 0.1 f 10 f 0.1 f ad8063 49.9 1k +4v 1 ? 4v 1k 10 f 0.1 f 10 f 0.1 f ad8063 01065-056 figure 57. ad8063 mux output figure 56. two-to-one multiplexer using two ad8063s
ad8061/ad8062/ad8063 rev. d | page 19 of 20 outline dimensions pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 1 3 4 5 2 0.22 0.08 10 5 0 0.50 0.30 0.15 max seating plane 1.45 max 1.30 1.15 0.90 2.90 bsc 0.60 0.45 0.30 compliant to jedec standards mo-178aa 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa figure 58. 5-lead small outline transistor package [sot-23] (rt-5) dimensions shown in millimeters figure 59. 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 1 3 4 5 2 6 2.90 bsc 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.22 0.08 10 4 0 0.50 0.30 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.60 0.45 0.30 pin 1 indicator compliant to jedec standards mo-178ab 0.80 0.60 0.40 8 0 4 8 1 5 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa figure 61. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters figure 60. 6-lead small outline transistor package [sot-23] (rt-6) dimensions shown in millimeters
ad8061/ad8062/ad8063 rev. d | page 20 of 20 ordering guide model temperature range package desc ription package option branding ad8061ar ?40c to +85c 8-lead soic r-8 ad8061ar-reel ?40c to +85c 8-lead soic, 13-inch tape and reel r-8 ad8061ar-reel7 ?40c to +85c 8-lead soic, 7-inch tape and reel r-8 ad8061arz 1 ?40c to +85c 8-lead soic r-8 AD8061ARZ-REEL 1 ?40c to +85c 8-lead soic, 13-inch tape and reel r-8 AD8061ARZ-REEL7 1 ?40c to +85c 8-lead soic, 7-inch tape and reel r-8 ad8061art-r2 ?40c to +85c 5-lead sot-23, 250 piece tape and reel rt-5 hga ad8061art-reel ?40c to +85c 5-lead sot-23, 13-inch tape and reel rt-5 hga ad8061art-reel7 ?40c to +85c 5-lead sot-23, 7-inch tape and reel rt-5 hga ad8061artz-r2 1 ?40c to +85c 5-lead sot-23, 250 piece tape and reel rt-5 h0d 2 ad8061artz-reel 1 ?40c to +85c 5-lead sot-23, 13-inch tape and reel rt-5 h0d 2 ad8061artz-reel7 1 ?40c to +85c 5-lead sot-23, 7-inch tape and reel rt-5 h0d 2 ad8062ar ?40c to +85c 8-lead soic r-8 ad8062ar-reel ?40c to +85c 8-lead soic, 13-inch tape and reel r-8 ad8062ar-reel7 ?40c to +85c 8-lead soic, 7-inch tape and reel r-8 ad8062arz 1 ?40c to +85c 8-lead soic r-8 ad8062arz-rl 1 ?40c to +85c 8-lead soic, 13-inch tape and reel r-8 ad8062arz-r7 1 ?40c to +85c 8-lead soic, 7-inch tape and reel r-8 ad8062arm ?40c to +85c 8-lead msop rm-8 hca ad8062arm-reel ?40c to +85c 8-lead msop, 13-inch tape and reel rm-8 hca ad8062arm-reel7 C40c to +85c 8-lead msop, 7-inch tape and reel rm-8 hca ad8062armz 3 ?40c to +85c 8-lead msop rm-8 #hca ad8062armz-rl 3 ?40c to +85c 8-lead msop, 13-inch tape and reel rm-8 #hca ad8062armz-r7 3 C40c to +85c 8-lead msop, 7-inch tape and reel rm-8 #hca ad8063ar C40c to +85c 8-lead soic r-8 ad8063ar-reel C40c to +85c 8-lead soic, 13-inch tape and reel r-8 ad8063ar-reel7 C40c to +85c 8-lead soic, 7-inch tape and reel r-8 ad8063arz 1 40c to +85c 8-lead soic r-8 ad8063arz-reel 1 40c to +85c 8-lead soic, 13-inch tape and reel r-8 ad8063arz-reel7 1 40c to +85c 8-lead soic, 7-inch tape and reel r-8 ad8063art-r2 C40c to +85c 6-lead sot-23, 250 piece tape and reel rt-6 hha ad8063art-reel C40c to +85c 6-lead sot-23, 13-inch tape and reel rt-6 hha ad8063art-reel7 C40c to +85c 6-lead sot-23, 7-inch tape and reel rt-6 hha ad8063artz-r2 1 C40c to +85c 6-lead sot-23, 250 piece tape and reel rt-6 h0e 4 ad8063artz-reel 1 C40c to +85c 6-lead sot-23, 13-inch tape and reel rt-6 h0e 4 ad8063artz-reel7 1 C40c to +85c 6-lead sot-23, 7-inch tape and reel rt-6 h0e 4 1 z = pb-free part. 2 new branding after data code 0542, previously branded hga. 3 z = pb-free part, # denotes lead-free product may be top or bottom marked. 4 new branding after data code 0542, previously branded hha. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c01065-0-12/05(d)

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